The timing of events is key to proper processing within user-defined logic devices. Accordingly, a single clock is used as a reference to determine the timing of events. Each process may be clocked from a single distributed clock signal, providing highly synchronized processing.
However, not all processes are active at all times. Therefore, some processes do not require a continuous clock signal. Continuously providing the primary clock signal to a process that does not require such adds unnecessarily to the power consumption of the chip. A significant cause of power consumption within a user-defined logic device is the power required to distribute the primary clock signal throughout the chip.
To lessen this power consumption, some users of user-defined logic devices utilize a portion of the resources of the logic device to "gate" the primary clock. A clock is gated when the regular clock pulse waveform is translated to a constant value output. For example, when a primary clock signal has a traditional square waveform, the gated clock signal has a constant logic value (e.g., a constant logic low value). Because the power required to provide a constant logic value to a process is less than the power required to provide a square waveform, the power consumption of the chip is reduced.
User-defined logic device resources typically use individual clock enable (CE) controls to control flip-flops and registers. These individual clock enable controls can be used to implement clock gating circuitry within the logic of the user-defined logic device. However, this method of gating the clock signal undesirably requires utilization of core logic resources of the user-defined logic device to form these clock enable controls.
Because flip-flops and registers respond to either the rising or falling edge of a clock signal, it would be desirable to have control over the state of the gated clock signal. Control over the state of the gated clock signal provides a user with control of the state of the flip-flops and registers receiving the gated clock signal. Thus, it would be desirable to control the logic value of the gated clock signal.
The high power consumption of a continuously running clock forces many users to create their own circuits to gate the global clock. This means that many users create their own methods of suspending the clock signal to a process to prevent the power consumption caused by the unnecessary provision of the primary clock to that process. These user-created methods can yield undesirable effects including glitches and runt pulses in the gated clock signal.
It would therefore be desirable to have a clock gating circuit for a user-defined logic device that does not consume large amounts of device resources, provides user control over the logic value of the gated clock, eliminates the need for users to define their own clock gating circuit, and eliminates undesirable clock signal disturbances, such as glitches and runt pulses.